1. Field of the Invention
The present application relates to polishing pads for chemical mechanical planarization (CMP) of substrates and, more particularly, to polishing pads customized for structures on the substrates.
2. Related Art
Chemical mechanical planarization (CMP) is used to planarize films on substrates, such as individual layers (dielectric or metal layers) during integrated circuit (IC) fabrication on a semiconductor wafer. CMP removes undesirable topographical features of the film on the substrate, such as metal deposits subsequent to damascene processes, or removal of excess oxide from shallow trench isolation steps.
CMP utilizes a reactive liquid medium and a polishing pad surface to provide the mechanical and chemical control necessary to achieve planarity. Either the liquid or the polishing surface (pad) can contain nano-size inorganic particles to enhance chemical reactivity and/or mechanical activity of the CMP process. The pad is typically made of a rigid, micro-porous polyurethane material capable of achieving both local and global planarization.
Conventional open-pore and closed-pore polymeric pads with essentially homogeneous tribological, chemical and frictional characteristics were previously suitable for CMP, until the introduction of 250 nm CMOS technology. For sub 250 nm technology with increased design complexity and associated chip pattern density variations, especially with increased chip size, the chip yields, device performance and device reliability have deteriorated significantly. Recent attempts by various pad vendors to change the thickness (stacked and unstacked) and surface grooving (perforated, K-groove, X-Y groove, and K-groove/X-Y groove combinations) of the pads have failed to address the impact that chip pattern density, chip size, complexity of architecture, and dielectric/metal process flow have on chip-level uniformity directly impacting chip yield, device performance and reliability of integrated circuits.